An electrically erasable and programmable nonvolatile semiconductor memory device is used for storing data in electronic systems. Such systems are typically equipped with an error correction code algorithm, as is well known in the art. If an error is generated in the system, it can be corrected via the error code algorithm, even though the error may be generated in a reading or writing operation of the nonvolatile semiconductor memory device. That is to say, the electronic system, which is equipped with the error correction code algorithm, allows containing the number of amendable fail bits.
The nonvolatile semiconductor memory device, in particular, NAND type flash memory device comprises an array consisting of plurality of array or memory blocks. In general, every manufactured memory array includes allowable bad blocks, which are not substantially used.
A test operation is performed on the packaged or completed NAND type flash memory device before this memory device is loaded. When the test operation is performed, such memory device should be discarded if it is determined that at least one of normal array blocks of the array have fail bit(s).
More particularly, if the number of fail bits of the array block found in the test operation does not exceed the number of amendable fail bits of the electronic system, the NAND type flash memory device having a bad block determined in the test operation can be used in the electronic system which is equipped with the error correction code algorithm. By keeping more of the manufactured memory devices, the yield can be improved.
There are a number of ways of testing the manufactured memory devices. Many packaged memory devices can be tested concurrently, to reduce testing time. Then, as the error capturing RAM of the test device simultaneously testing the packaged memory devices is limited, a total test result is stored in the error capture RAM of the test device. According to this test scheme, such an array block is determined as a bad block, if at least one bit is failed in each array block of the respective packaged memory device. The problem with this technique is that it is impossible to verify the number of fail bits in the array block determined as the bad block.
In another way of testing, the fail bits are counted one by one in each test process by using software. That is, the exact number of fail bits of each memory device can be counted by storing the test result corresponding to every memory cells to the error capture RAM of the test device. The problem, however, with such a software scheme is that, as the error capture RAM of the test device is limited, the number of the memory devices that can be tested simultaneously is reduced. This means that overall test time must be increased.
A need remains for determining exactly the number of fail bits of the memory device accepted in the electronic system, so that the memory device determined as a bad chip in a test operation may be available.